Solid electrolytic capacitors have been required to be reduced in size and increased in capacitance with the reduction in size and thickness for electrical and electronic devices, and furthermore, required to be reduced in leakage current in terms of product safety.
Laminate-type solid electrolytic capacitors have been known as one measure for responding the request for reduction in size and increase in capacitance. Conventionally, a method of obtaining a laminate chip of solid electrolytic capacitor elements by integrally preparing a plurality of solid electrolytic capacitor elements in a sheet form, and stacking and then cutting the thus obtained plurality of sheets is known as a method for manufacturing the solid electrolytic capacitors (see Patent Document 1). More specifically, first, a valve-acting metal substrate (with a surface subjected to no surface roughening) is prepared which includes a plurality of rectangular regions corresponding to solid electrolytic capacitor elements, a resist layer is formed so as to cover the vicinity of at least three sides of these plurality of rectangular regions, the region of the valve-acting metal substrate, which is exposed from the resist layer, is made porous by applying surface roughening to the region, a dielectric layer is formed on the surface of the porous region, and a solid electrolyte layer is then formed as a cathode material layer, thereby providing a sheet that has a plurality of solid electrolytic capacitor elements integrally prepared. A plurality of the sheets are prepared, these sheets are stacked and fixed to form a laminate, and this laminate is cut to follow the rectangular regions corresponding to solid electrolytic capacitor elements, thereby providing a laminate chip of solid electrolytic capacitor elements.
Patent Document 1: JP 2007-318056 A